Field of the Invention
The present invention relates to a clock generator, and particularly relates to a voltage controlled oscillator.
Description of the Related Art
A clock generator including a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) has generally been used for generating a clock having a predetermined frequency. The voltage controlled oscillator is a circuit that controls an oscillation frequency of a clock depending on the electric potential applied externally. In a case of use in a semiconductor integrated circuit specialized in a specific function (for example, ASIC: Application Specific Integrated Circuit or ASSP: Application Specific Standard Product), a clock generator is often required to be capable of regulating or adjusting a phase of a clock. Such a semiconductor integrated circuit is needed in many fields such as information appliances and automobile electronics, and therefore, the clock generator capable of regulating the phase of the clock is mainly used in the current information society.
As a clock generator capable of regulating a phase of a clock, there is a clock generator including a ring type voltage controlled oscillator. Such a ring type voltage controlled oscillator is configured by multiple inverters connected in a ring shape. The ring type voltage controlled oscillator oscillates at a frequency based on a voltage to be given externally, and outputs clocks with different phases from one another, from the differential inverters. The clock generator including such a ring type voltage controlled oscillator selects and outputs, with a multiplexer, either of the clocks with different phases from one another that are output by the differential inverter circuits, and thereby outputs a clock having an arbitrary phase.
For example, Japanese Patent Publication No. 2010-206344 discloses a clock generator having a spread spectrum function. The clock generator disclosed in Japanese Patent Publication No. 2010-206344 includes multiphase clock generation means for generating multiphase clock signals based on a phase difference between a reference clock signal and a feedback clock signal and outputting two clock signals having adjacent phases, modulated waveform data storage means for storing modulated waveform data in which a phase step for frequency modulation changes stepwise, correction means for outputting phase correction data for correcting the phase at each phase step of the modulated waveform data, and phase interpolation means for interpolating the phase between the two clock signals based on the phase correction data and the modulated waveform data, generating an interpolated clock signal, and supplying the interpolated clock signal to the multiphase clock generation means.
Further, for example, Japanese Patent Publication No. 2007-228043 discloses a digital DLL (Delay Locked Loop) circuit. The digital DLL circuit disclosed in Japanese Patent Publication No. 2007-228043 includes a register to retain a delay target value, an oscillator, a first counter to count an external reference clock or the oscillatory output of the oscillator for determining a measurement cycle, a second counter to count the oscillatory output of the oscillator or the external reference clock in the measurement cycle determined by the first counter, a digitally controlled variable delay circuit, and a controller to control the reset, start and furthermore, as necessary, stop of the first counter and the second counter based on the count value of the first counter, to perform a digital operation for the count value of the second counter and the delay target value of the register, and to give the operation result to the variable delay circuit as a delay control value.
The above-described clock generator disclosed in Japanese Patent Publication No. 2010-206344 and the above-described clock generator included in the digital DLL disclosed in Japanese Patent Publication No. 2007-228043 both used a multiplexer for obtaining a clock having an arbitrary phase. Therefore, such conventional clock generators has a problem in that the electric power consumption of the whole chip increases because a high-speed clock is input to the multiplexer. Further, the conventional clock generators has a problem in that the controller (i.e., the multiplexer) connected at each output stage of the voltage controlled oscillator exerts an adverse influence on the oscillation frequency of the voltage controlled oscillator by its own parasitic capacitance. Furthermore, the conventional clock generators has a problem in that it is difficult to regulate the phase of the clock with a high accuracy because a separate circuit is required for regulating a further finer phase than the phase of the clock to be output by each output stage of the voltage controlled oscillator.
Hence, the present invention has an object to provide a clock generator that can regulate a phase of a clock with a low electric power consumption.
Further, the present invention has an object to provide a clock generator that can regulate a phase of a clock with a high accuracy.
Furthermore, the present invention has an object to provide a clock generator that can reduce influence of a controller on the oscillation frequency of the clock.